The present invention relates to a static memory using an insulating gate type field effect transistor (MIS FET).
FIG. 1 shows an example of a bit line circuit section corresponding to each column of a memory cell array in a conventional static memory. A pair of bit lines BL and BL are connected to power supply terminal V.sub.DD through normally-ON p-channel pull-up load transistors Q1 and Q2. Bit lines BL and BL are also connected to a pair of write data lines din and din through n-channel transmission gate transistors Q3 and Q4 which are controlled to be selected by column selection signal CD. Bit lines BL and BL are connected to common data lines CL and CL through p-channel transmission gate transistors Q6 and Q7 which are controlled to be selected by inverted column selection signal CD, and are also connected to sense amplifier SA. P-channel equalize transistor Q5, which is controlled to be selected by bit line equalize signal .phi.BEQ, is connected between bit lines BL and BL. A plurality of static memory cells MC are parallel-connected between bit lines BL and BL. Each memory cell MC comprises n-channel drive transistors Q8 and Q9 constituting a flip-flop circuit and their load resistors R1 and R2, and n-channel transmission gate transistors Q10 and Q11 connected between a pair of I/O terminals of the flip-flop circuit and bit lines BL and BL, as shown in FIG. 1. The gates of transistors Q10 and Q11 are connected to identical word line WL.
The read mode of the static memory cell with the above structure will now be described with reference to the timing chart shown in FIG. 2. Transistor Q5 is turned on in response to bit line equalize signal .phi.BEQ which is generated before a word line selection operation is started in response to an internal clock signal generated based on a change in an external input signal such as an address input. When transistor Q5 is turned on, the potentials of the bit lines are pulled up to power supply voltage level V.sub.DD by pull-up load transistors Q1 and Q2 while being equalized.
When one of word lines WL is selected, low-potential (L-level) drive transistor Q9 and transmission gate transistor Q11, connected in series with transistor Q9 in memory cell MC connected to selected word line WL, are respectively turned on. When transistors Q9 and Q11 are turned on, the potential of L-level bit line BL is decreased to an intermediate potential between power supply potential VDD and ground potential V.sub.SS.
In contrast to this, high-potential (H-level) bit line BL is left at the power supply potential, and potential difference .DELTA.V is generated across the bit lines. Since transistors Q6 and Q7 of the selected column are turned on by inverted column selection signal CD before word line selection, potential difference .DELTA.V across the bit lines is transmitted to common data lines CL and CL through transistors Q6 and Q7 and is input to sense amplifier SA to be differentially amplified in this selected column.
At this time, a direct current flows through a current path consisting of power supply terminal V.sub.DD, L-level pull-up load transistor Q2, bit line BL, transistor Q11 of memory cell MC, transistor Q9, and ground terminal V.sub.SS. For this reason, a change rate of the potential of L-level bit line BL becomes low, since discharging by a pull-in current is cancelled by charging of the direct current. As a result, an increase in potential difference .DELTA.V across the bit lines is disturbed, and its increase rate becomes low. Thus, the sense operation of the sense amplifier becomes slow.
In this case, pull-up load transistors Q1 and Q2 associated with the level of the direct current are provided to limit voltage amplitudes of bit lines BL and BL so that the above-mentioned pull-up/equalize operation of bit lines BL and BL is accelerated.
Therefore, in the conventional static memory cell, the sizes of pull-up load transistors Q1 and Q2 must be determined to optimize the speeds of the sense operation and the pull-up/equalize operation.
In the above read mode, transistors Q3 and Q4 are selected by column selection signal CD in the selected column. However, write data lines din and din are controlled to be kept at a voltage level equal to the power supply potential V.sub.DD in the read mode. Therefore, transistors Q3 and Q4 cannot be turned on until the bit line potentials are decreased from power supply potential V.sub.DD to the threshold voltages of transistors Q3 and Q4. For this reason, transistors Q3 and Q4 do not contribute to the sense operation. In a nonselected column, transistors Q3 and Q4 are kept off, and no sense operation is performed.
The write mode of the bit line circuit section will now be described with reference to the timing chart shown in FIG. 3. Column selection and word line selection are performed after the bit lines are equalized and pulled up in the same manner as in the read mode, and predetermined memory cell MC is selected. One (in this case, din) of write data lines din and din is kept at power supply potential V.sub.DD level and the other (in this case, din) is pulled down to the ground potential. Thus, in the selected column, transistors Q3 and Q4 are turned on, so that bit lines BL and BL are respectively set at the power supply potential V.sub.DD level and the ground potential. In this manner, write control for memory cell MC is performed.
In a nonselected column, since transistors Q3, Q4, Q6, and Q7 are turned off, the potentials of bit lines BL and BL are changed in accordance with the data content of the memory cell selected by word line WL.
In the write mode as described above, the direct current flows through a path consisting of power supply potential V.sub.DD, L-level pull-up load transistor Q2 in the selected column, bit line BL, write control transistor Q4, and write data line din. In this case, since the direct current is determined by the driving power of pull-up drive transistor Q2, it is increased several times that in the read mode, and causes an increase in power consumption in the write mode.
As described above, in the bit line circuit section of the conventional static memory shown in FIG. 1, a DC current flows through the bit lines of the selected column in a read cycle by the normally-ON type p-channel pull-up load transistor which is provided to limit the bit line amplitude. As a result, an increase rate of bit line potential difference .DELTA.V becomes low, and the high-speed sense operation is disturbed. In the write cycle, a direct current several times that in the read mode flows through the bit lines of the selected column and this results in an increase in current consumption.
FIG. 4 shows a bit line circuit section in another conventional static memory. The same reference numerals in this figure denote the same parts as in FIG. 1, except that the bit line circuit section of this figure has p-channel precharge transistors Q12 and Q13 which are respectively connected in parallel with pull-up load transistors Q1 and Q2 and controlled to be selected by bit line precharge/equalize signal .phi.BEQ, and a bit-line precharge/equalize circuit is constituted by transistors Q12 and Q13 and equalize transistor Q5.
The basic operation of the bit line circuit section shown in FIG. 4 is substantially the same as that in FIG. 1. When precharge transistors Q12 and Q13 are turned on during the equalize operation, the current drive power of the load transistors in the column is enhanced. As a result, the precharge/equalize operation can be performed at higher speed than that in FIG. 1. Therefore, the circuit can be designed such that the current drive power of pull-up load transistors Q1 and Q2 is weakened by a degree corresponding to the current drive power of pull-up transistors Q12 and Q13. For this reason, a delay of an increase in potential difference across the bit lines in the read mode and an increase in power consumption due to the direct current in the selected column in the write mode can be slightly suppressed. However, the above problems cannot be satisfactorily solved.
It is an object of the present invention to provide a static memory capable of realizing a high-speed read operation, and of realizing low power consumption by removing a direct current component in a selected column in a write mode.